The present invention relates to a bus line drive circuit in a computer system of the type in which data is transferred through a bus line or lines.
In an integrated circuit (IC) forming a computer system, particularly in a large scale integrated circuit (LSI) forming a microcomputer system, bus lines are frequently used for data transfer. A prior bus line drive circuit for transferring data through a bus line is shown in FIG. 1. The bus line drive circuit is comprised of N-channel MOSFETs (metal oxide semiconductor field effect transistors) coupled with bus lines DB0 to DB3 for four bits, which are generally designated by reference numeral "1". The bus lines DB0 to DB3 are coupled with a precharge circuit 2 and an input/output (I/O) device 3 further connected to an arithmetic logic unit (ALU) 4, for example. The I/O device 3 is used as an interface circuit for transferring data between the ALU 4 and another ALU (not shown) through the bus line 1. The precharge circuit 2 precharges the bus line 1 every state (period) T, as shown in FIG. 2B. In operation, a clock pulse .phi.p (FIG. 2A) for precharge is applied to the gates of MOS transistors T5 to T8 constituting the precharge circuit 2. When the pulse .phi.p is in "1" level, the MOSFETs T5 to T8 are ON (in a low impedance state). And the currents flowing through the MOSFETs T5 to T8 charge bus lines DB0 to DB3 up to "1" level. When the pulse .phi.p is in "0" level, the MOSFETs T5 to T8 are OFF (in a high impedance state). During this period, no charge current flows, so that the bus lines DB0 to DB3 are not charged. Thus, the period that the pulse .phi.p is in "1" level is a precharge time, while the period that it is in "0" level is a non-precharge period, or an active period for the data transfer. The output MOSFETs T1 to T4 of the I/O device 3 constitute an output section of the I/O device 3. The output transistors T1 to T4 of the I/O device 3 are controlled so as to have a high impedance during the precharge period by the control gate (not shown) in the ALU 4. During an active period, the control gate so controls the transistors T1 to T4 to have a low impedance when the data to be outputted is "0" and to have a high impedance when the data is " 1". Transistors T9 to T12 and inverters IVl to IV4 connected to the MOS transistors T9 to T12 made up an input section of the I/O device 3. The input section is electrically coupled with the bus line 1 only during the active period for writing data by a clock signal .phi.w (FIG. 2C) applied to the gates of MOS transistors T9 to T12. During other periods, it is electrically disconnected from the bus line.
In an ordinary LSI, a number of I/O devices 3 are contained, but only one precharge circuit 2 is contained. Accordingly, even when the widths of the precharge transistors T5 to T8 are slightly widened to increase the conductance of the transistors T5 to T8 and finally to increase a charging speed, the overall area of the LSI is not so much increased. An ordinary LSI contains at least 10 output transistors T1 to T4 in the I/O device 3. Some LSIs contain 30 or more output transistors. For increasing the operating speed, the widths of these transistors T1 to T4 are selected to be relatively wide in the circuit design. For these reasons, the prior art involves some problems. The increase of the chip size is unavoidable. A parasitic capacitance of the bus line is increased since the area of the drain region is large, resulting in an adverse effect on the increase of the operation speed in the bus line drive circuit.